1. Field of the Invention
The present invention relates to technologies for isolating devices in integrated circuits and, in particular, to a poly coated sidewall-masked isolation technology.
2. Related Art
Integrated circuits are formed by interconnecting isolated devices through particular electrical paths. As a result, isolation technology is an important aspect of fabricating integrated circuits.
Since different integrated circuits have different isolation requirements, various techniques have been used to isolate devices. These various isolation techniques exhibit different attributes, with respect to minimum isolation spacing, surface planarity, process complexity, and density of defects generated during fabrication of the isolation structure. Tradeoffs can be made among these characteristics when selecting an isolation technology for a particular circuit application.
Generally, different isolation techniques are used for metal oxide semiconductor (MOS) devices and bipolar devices. Two common junction isolation techniques used in bipolar devices, are the standard buried collector (SBC) process and the collector diffused isolation (CDI) process. However, these techniques exhibit several disadvantages. Both processes utilize isolation diffusions which cause large collector-to-base and collector-to-substrate capacitances, which reduce the speed of the circuit.
In addition, both processes result in low collector-base junction breakdown voltages which limits the use of these circuits to applications requiring small power-supply voltages. The SBC process has the added disadvantage that wide isolation regions correspond to large inactive areas on the silicon surface, which can limit the packing density of the integrated circuit.
One standard industry technique used to isolate devices in p-channel MOS (PMOS) and n-channel MOS (NMOS) integrated circuits is LOCOS (LOcal Oxidation of Silicon). This technique involves forming a semirecessed oxide in the nonactive (or field) areas of the substrate.
A typical sequence of the operations involved in a conventional semi-recessed LOCOS technique is shown in FIGS. 1A-1D. The first step involves thermally growing a silicon dioxide (SiO.sub.2) layer 101 on the surface of a substrate 103 of a semiconductor silicon wafer 100, as shown in FIG. 1A. This silicon dioxide layer 101, is often referred to as the pad or buffer oxide, since it operates to cushion the transition of stresses between the silicon substrate and the subsequently deposited nitride layer. In an alternative technique a CVD (chemical vapor deposition) Si0.sub.2 is used instead of thermal Si0.sub.2.
Next, referring to FIG. 1B, a layer of silicon nitride (Si.sub.3 .sub.4) 105 is deposited on the silicon dioxide layer 101 and photolithography is used to pattern the two layers 101, 105, so that the desired isolation areas 107 are exposed, and the desired active areas 109 (i.e., those regions of the integrated circuit where active devices are to be formed) are covered with an oxidation barrier. The silicon nitride layer 105 is then dry etched, and the pad oxide 101 and the silicon substrate 103 are etched by means of either a dry or a wet chemical process, to form an isolation trench 113.
Subsequently, a field oxide 111 is thermally grown on the exposed silicon regions by using high-pressure oxidation (HIPOX), as shown in FIG. 1C. The field oxide 111 grows where there is no masking nitride 105. However, at the edges of the nitride 105, some oxygen diffuses laterally causing the field oxide 111 to grow under and lift these nitride edges. This encroachment of the field oxide layer 111 under the nitride layer 105 causes a tapering oxide wedge that merges into the pad oxide 101, and is referred to as a "bird's beak." Finally, the masking layer 105 is removed, as shown in FIG. 1D.
The conventional semi-recessed LOCOS isolation process described above has the disadvantage of leaving a bird's beak, which causes unacceptably large encroachment of the field oxide into the device active regions. This in turn reduces the packing density and active area available for making the devices. In addition, the growth of the field oxide in the trench causes stresses that can lead to defects in the silicon. Typically, defect-generating stresses arise at the bottom comers of the etched grooves during field oxide growth and are due to the volume expansion of the growing oxide.
First, as the oxide grows, its top surface is pushed outward by the newly forming oxide layer at the silicon substrate and silicon dioxide (SiO.sub.2) interface. This volume expansion causes tangential stresses in the corners of the trench. Second, as the laterally encroaching oxide grows under the nitride, it is restrained from growing upward by the stiffness of the nitride layer, causing further stress downward against the silicon in the corner of the recess. These stresses, if not relieved, can generate dislocations in the silicon such as line defects and stacking faults.
Another conventional isolation technique is the sidewall-masked isolation (SWAMI) technique, as shown in FIGS. 2A-2F. This technique offers two significant advantages over the conventional semi-recessed LOCOS: reduction of the bird's beak structure and an increase in packing density due to the reduction of lateral oxide encroachment. This technique involves forming a pad-oxide layer 101 and a CVD-nitride layer 105 on top of the silicon substrate 103, and then etching these three layers in the same manner as in conventional Semi-recessed LOCOS to form isolation trench 113, as shown in FIGS. 1A-1B.
Subsequently, as shown in FIG. 2A, a second stress-relief oxide layer 201 is grown followed by the deposition of a second CVD nitride layer 203, which provides conformal coverage of the entire surface, including the sidewalls of the silicon trench 113. Then a CVD oxide 205 is deposited on the second CVD nitride layer 203, as shown in FIG. 2B. All three layers 201, 203, 205 are then anisotropically etched in the field region such that the layers 201, 203, 205 remain only on the sidewalls of the trench and in the corners of the trench (foot), as shown in FIG. 2C. The CVD oxide 205 forms a spacer that protects only part of the second nitride layer 203, and this nitride layer 203 forms a structure with a foot that extends partway into the exposed silicon at the bottom of the trench 113. Typically, the oxide sidewall spacer 207 is removed. After the oxide spacer has been etched away, the final structure is a silicon mesa whose sidewalls are surrounded by the second nitride layer 203 and oxide 201, as shown in FIG. 2D.
In the next step, the field oxide is grown and the thin sidewall nitride 203 is bent upward due to the expansion of the converted SiO.sub.2 oxide 211, as shown in FIG. 2E. As the oxide expands, the sidewall nitride 203 continues to bend upward as shown in FIG. 2F. Finally the masking nitride layers are removed. This process reduces the bird's beak structure and achieves a relatively planar surface topography.
Although this process is an improvement over the conventional LOCOS isolation technique, this process has some disadvantages. First, the sidewall nitride 203 rises during oxidation, allowing for some encroachment although it is less than that in conventional LOCOS. In addition, this process yields excessive stresses at the corners of the trench, since oxide growth in that region is restrained due to nitride compression.
Another technique for eliminating the bird's beak is described in an article entitled "New Techniques for Elimination of the Bird's Head and Bird's Beak," by Burton et al., 1984, IEDM, pp. 582-585, hereby incorporated by reference. This article discloses a field isolation method requiring two processing steps in addition to the conventional recessed isoplanar process, namely (1) a polysilicon sidewall spacer formation and (2) an oxide "bump" planarization. A polysilicon sidewall is used to reduce oxide encroachment during the field oxidation step. The process sequence is shown in FIGS. 1A-1B and 3A-3E.
The first steps of the technique are analogous to those shown in FIGS. 1A-1B. Subsequently, a second oxide layer 301 is grown on the trench, as shown in FIG. 3A. However, before a regular field oxidation in a recessed isoplanar technique, a polysilicon sidewall spacer 305 is formed along the sidewall of the trench region by low pressure chemical vapor deposition (LPCVD), polysilicon deposition 303 and anisotropic etchback (FIGS. 3B and 3C).
During the subsequent field oxidation, the outer layer of polysilicon along the sidewall is oxidized first and transformed into silicon dioxide 309. This method works in such a way that oxidation at the silicon nitride/silicon dioxide/silicon interface does not take place until the polysilicon sidewall spacer 305 is completely oxidized into silicon dioxide 309. The polysilicon spacer 305, by virtue of the delaying action, allows for the bird's beak to be reduced to a zero value as shown in FIG. 3D.
The oxidation of the polysilicon sidewall generates an oxide "bump" 307 at the boundary between field and active region as shown in FIG. 3D. This undesirable protrusion can be removed using some available planarization technique to yield the resulting structure shown in FIG. 3E.
Although this process sequence is an improvement over the conventional LOCUS process sequence, this process sequence requires a difficult planarization scheme.
Thus, a need exists to increase the packing density on an integrated circuit, eliminate oxide encroachment without requiring a difficult planarization scheme, and minimize the formation of stresses in the silicon, while maintaining a short processing time and low processing cost.